The present invention relates to a memory device, i.e., to a semiconductor integrated circuit in which the memory cells are integrated. More specifically, the invention relates to a sense amplifier circuit technology integrated with the memory cells to amplify a pair of complementary signals having a minute potential difference and read out from a memory cell.
As used in this application, inversion refers to the change of a data line from one of a high and low to the other of a high and low in adjacent read cycles, that is, the signal on the data line inverts from one read cycle to the next.
A conventional sense circuit for amplifying a read out signal from a memory cell has been disclosed in Japanese Laid-Open Patent Specification No. 52-8734 as shown in FIG. 3, in which complementary pair input signals d, dNOT are connected to the gate and drain of two cross-coupled driver MOS transistors, Q13 and Q14 in a sense amplifier circuit with load MOSFET's Q.sub.11 and Q.sub.12, and the drains of the above two driver MOS transistors Q.sub.13 and Q.sub.14 respectively serve as complementary pair output signals D, DNOT.
Further, according to U.S. Pat. NO. 4,335,449, as shown in FIG. 4, there are two cross-coupled load MOS transistors Q.sub.21 and Q.sub.22 connected to bipolar drive transistors Q.sub.23 and Q.sub.24 that receive complementary pair input signals d, dNOT connected to the base. The two driver bipolar transistors Q.sub.23 and Q.sub.24 have emitters connected through transistor Q.sub.25 under control of signal SAC and through MOSFET Q.sub.26 to ground.